1. Field of the Invention
The present invention relates to a device and method for varying a bit line precharge voltage in a semiconductor memory, and more particularly, to a device and method for varying a bit line precharge voltage in a semiconductor memory, in which the bit line precharge voltage is varied with a chip temperature for improving a refresh characteristic, reducing power consumption.
2. Background of the Related Art
FIG. 1 illustrates a circuit showing a system of a related art DRAM.
Referring to FIG. 1, the related art DRAM is provided with a cell array unit 10 having word lines WLi and WLj each for applying an address signal thereto in input/output of a data to/from the DRAM, bit lines Bl and bit bar lines BLb each for input/output of the data, cell capacitors C1 and C2 for storing the data thereto, and transistors MN1 and MN2 adapted to be turned on/off in response to the address signal on the word lines WLi and WLj for reading/recording the data from/in the cell capacitors C1 and C2 through the bit lines Bl and bit bar lines Blb, a sense amplifier 20 for sensing and amplifying the data stored in each cell in the cell array unit 10 and provided through the bit lines, a driving unit 30 for providing a driving signal to the sense amplifier 20 for improving a sensitivity of the sense amplifier 20, and a data output circuit(not shown) for receiving the data from the sense amplifier 20 through the bus lines (not shown), amplifying at a given amplification ratio, and forwarding to outside of the DRAM.
The operation of the aforementioned related art DRAM will be explained. FIG. 2 illustrates a waveform showing changes of level of a V.sub.DD voltage provided to the memory cell array. Of the basic operations of write, read, and refresh of the DRAM, the read operation is proceeded as follows.
Upon reception of, for example, an address signal, since a word line WL for the address signal is selected to bootstrap the WL to a high voltage and turn on the transistor MN1 connected to the selected word line WL, a cell data stored in the cell capacitor C1 is moved to the bit line BL. Then, the sense amplifier 20 senses and amplifies the data, and transfers to the data bus line. Eventually, the data output circuit(not shown in FIG. 1) receives the data from the bus line, amplifies to a given amplification ratio, and forwards to outside of the DRAM.
The foregoing operation will be explained further in detail.
Referring to FIG. 2, a VBLP(Bit Line Precharge Voltage) and a VCP(Cell Plate Voltage) are 1/2V.sub.DD, respectively. Therefore, upon a word line WL is selected in response to an address signal, the selected word line WLi is enable at a high voltage. When the word line WL is enabled, turning on the transistor MN1 connected to the enabled word line WLi, a parasitic capacitor Cb of the bit line and the cell capacitor C1 make charge sharing through the turned on transistor MN1. If it is assumed that the cell capacitor C1 is in storage of a V.sub.DD level voltage which is data "1", a level of the bit line BL becomes higher than a level of the bit bar line BLb by .DELTA.Vb1 as expressed in equation (1), below. Opposite to this, if the cell capacitor C1 is in storage of data "0", the level of the bit line BL becomes lower than a level of the bit bar line BLb by .DELTA.Vb0 as expressed in equation (2), below. Therefore, from equations (1) and (2) and VBLP is 1/2V.sub.DD as expressed in equation (3), it can be known from equation (4) that an absolute value of a variation of the level of the bit line is equal, according to "1" or "0" of the cell data.
If the cell data is V.sub.DD, EQU .DELTA.Vb1=[C1/Cb*V.sub.DD -C1/Cb*VBLP]/(1+C1/Cb) (1)
On the other hand, if the cell data is "0", EQU .DELTA.Vb0=-(C1/Cb*VBLP)/(1+C1/Cb) (2) EQU VBLP=V.sub.DD /2 (3) EQU .DELTA.Vb1=-.DELTA.vb0 (4)
Here, implications of the refresh operation will be explained. The data stored in a form of a charge in an isolated cell capacitor is diminished due to a leakage current caused by imperfect capacitor. Therefore, a repetitive process in which the stored data is read out, and the data is written again before complete extinction of the data is required, which is called as the refresh operation. The refresh operation should be executed before determination of the signal stored in the memory capacitor of being "1" or "0" becomes impossible due to excessive discharge of the signal charge, of which period is called a refresh period. And, a number representing times of a cycle in which entire rows of the DRAM are selected and refreshed is called a refresh cycle. A refresh interval is the refresh period divided by the refresh cycle. In an early stage of semiconductor device development, the refresh interval is substantially constant. However, as packing densities of the semiconductor devices become greater, with an increased number of bits which should be operated within one cycle period, a power consumption is increased.
In order to solve such problems, a related art device for controlling the refresh period as shown in FIG. 3 is suggested. FIG. 3 illustrates a block diagram of a related art device for controlling a refresh period, and FIG. 4 illustrates waveforms at different units in the device shown in FIG. 3.
Referring to FIG. 3, the related art device for controlling a refresh period is provided with a temperature detector 40 fitted on the chip for detecting a chip temperature and providing a detecting signal TMP-DET, a Vcc voltage detector 50 for detecting and forwarding a level of a constant voltage Vcc, a reset counter 70 for counting a PSRP(Programmable Self Refresh Pulse) clock signal and providing a signal of given bits for resetting the PSRP clock signal, and a rest signal controller 60 for receiving a signal from the reset counter 70, providing an ISRP (Internal Self Refresh Pulse) signal which determines a period of a reset signal according to the temperature detecting signal TMP-DET detected at the temperature detector 40 and the Vcc voltage detected value detected at the Vcc voltage detector 50, and providing a signal for resetting the reset counter 70.
The operation of the aforementioned related art device for controlling a refresh period will be explained.
As a retention time period of a cell data is relatively reduced in a case when a temperature is high or a Vcc is low in comparison to a case when the temperature is low or the Vcc is high, the refresh period of the chip is made faster, for preventing malfunction of the cell data. That is, it is assumed that the reset counter 70 counts PSRP and provides three bit of data of 000 to 111. The reset signal controller 60 determines the signal TMP-DET from the temperature detector 40 and the signal Vcc-DET from the Vcc voltage detector 50, to provide a reset signal when an output of the reset counter 70 is 111 in the case the chip temperature is low and the Vcc voltage is high, to provide the reset signal when the output of the reset counter 70 is 100 in the case the chip temperature is high or the Vcc voltage is low, and to provide the reset signal when the output of the reset counter 70 is 001 in the case the chip temperature is high and the Vcc voltage is also high. When the reset signal controller 60 is operative thus, at the end, the reset signal is provided in a period identical to the PSRP in the case the chip temperature is high and the Vcc is low, the reset signal is provided at every four PSRP pulses(because the reset signal is provided when the output of the reset counter is 100) in the case the chip temperature is high or the Vcc voltage is low, and the reset signal is provided at every seven PSRP pulses(because the reset signal is provided when the output of the reset counter is 111) in a normal case the chip temperature is low and the Vcc voltage is high.
However, the related art device for controlling a refresh period has the following problems.
Referring to FIG. 4, as the chip temperature is the higher or the Vcc voltage is the lower, the retention time period of the cell data is the shorter, and the retention time period of the cell data is the shorter as the level of data stored in the cell capacitor is the higher, rather than the lower. For example, it is assumed that a high data "1" and a low data "0" are varied at different rates in a turn off of the cell transistor and stored as Vc1 and Vc0, respectively. When develop voltages are obtained using charge sharing equations (1) and (2), it can be known that a size of .DELTA.V1 of the high data "1" is smaller than a size of .DELTA.V0 of the low data "0" according to the following equations.
If the cell data is V.sub.DD -.DELTA.1=Vc1, EQU .DELTA.Vb1=[C1/Cb*.DELTA.Vc1-C1/Cb*VBLP]/(1+C1/Cb) (5)
On the other hand, if the cell data is 0+.DELTA.0=Vc0, EQU .DELTA.Vb0=[C1/Cb*Vc0-C1/Cb*Vblp]/(1+C1/Cb) (6)
If an absolute value of .DELTA.1 is greater than an absolute value of .DELTA.0(.vertline..DELTA.1.vertline.&gt;.vertline..DELTA.0.vertline.), a relation of the equations (5) and (6) can be expressed with an inequality (7), below. EQU .vertline..DELTA.Vb1.vertline.&lt;.vertline..DELTA.Vb0.vertline.(7)
The inequality (7) implies that, as explained in association with the related art, if the data on the bit line is detected using 1/2 Vdd voltage, a refresh characteristic of the data can not but be asymmetric. And, varying the refresh period without taking the fact that the refresh period is asymmetric into consideration leads to consume a power more than necessary.